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quad 64 - /256 - position i 2 c nonvolatile memory digital potentiometers data sheet a d5253 / ad5254 rev. c document feedback i nformation furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifi cations subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. b ox 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2003 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features ad5253: quad 64 - position resolution ad5254: quad 256 - position resolution 1 k? , 10 k ? , 50 k ? , 100 k ? nonvolatile memory 1 stores wiper settings w / write protection power - on refreshed to eemem settings in 300 s typ eemem rewrite time = 540 s typ res istance tolerance stored in nonvolatile memory 12 extra bytes in eemem for user - defined information i 2 c - compatible serial interface direct read/write access of rdac 2 and eemem registers predefined linear increment/decrement commands predefined 6 db step c hange commands synchronous or asynchronous quad - channel update wiper setting readback 4 mhz bandwidth 1 k? version single supply 2.7 v to 5.5 v dual supply 2.25 v to 2.75 v 2 slave address - decoding bits allow operation of 4 devices 100- year typical data retention, t a = 55c op erating temperature: C 40c to +10 5c applications mechanical potentiometer replace ment low resolution dac replacement rgb led backlight control white led brightness adjustment rf base station power amp bias control programmable gain and offset control programmable attenuators programmable voltage - to - current conversion programmable power supply programmable filters sensor calibrations general description the ad5253/ad5254 are quad - channel, i 2 c ? , nonvolatile mem - ory, digitally controlled potentiometers with 64/256 positions, respectively. these devices perform the same electronic adjust - me nt functions as mechanical potentiometers, trimmers, and variable resistors. the part s versati le programmability allows multi ple modes of operation, including read/write access in the rdac and eemem registers, increment/decrement of resistance, resistance changes in 6 db scales, wiper setting readback, and extra eemem f or storing user - defined informa tion, such as memory data for other components, look - up table, or system identification information. functional block dia gram rdac0 regis- ter rdac1 regis- ter rdac2 regis- ter rdac3 regis- ter rdac0 rdac1 rdac2 rdac3 data control command decode logic address decode logic control logic ad5253/ad5254 i 2 c serial interface v dd a0 w0 b0 a1 w1 b1 a2 w2 b2 a3 w3 b3 v ss dgnd scl sda ad0 ad1 wp 03824-0-001 eemem power-on refresh r ab tol rdac eemem figure 1. the ad5253/ad5254 allow the host i 2 c controllers to write any of the 64 - /256 - step wiper settings in the rdac registers and store them in the eemem. once the settings are stored, they are restored automatically to the rdac registers at system power - on ; the settings can also be restored dynamically. the ad5253/ad5254 provide additional increment, decrement, +6 db step change, and C 6 db step change in synchronous or asynchronous channel update mode. the increment and decrement functions allow stepwise li near adjustments, with a 6 db step change equivalent to doubling or halving the rdac wiper setting. these functions are useful for steep - slope, nonlinear adjustments , such as white led brightness and audio volume control. the ad5253/ad5254 have a patente d resistance - tolerance storing function that allows the user to access the eemem and obtain the absolute end - to - end resistance values of the rdacs for precision applications. the ad5253/ad5254 are available in tssop - 20 packages in 1 k ?, 10 k?, 50 k?, and 100 k? options. all parts are guaranteed to operate over the C 40c to +10 5c extended industrial temperature range. 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital potentiometer and r dac are used interchangeably.
ad5253/ad5254 data sheet rev. c | page 2 of 32 table o f contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 electrical characteristics ................................................................. 3 1 k ? ve rsion .................................................................................. 3 10 k?, 50 k?, 100 k? ve rsions .................................................. 5 interface timing characteristics ................................................ 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configuration and function descriptions ............................. 9 typical performance characteristics ........................................... 10 i 2 c interface ..................................................................................... 14 i 2 c interface general description ............................................ 14 i 2 c interface detail description ............................................... 15 i 2 c - compatible 2 - wire serial bus ........................................... 20 theory of operation ...................................................................... 21 linear increment/decrement commands ............................. 21 6 db adjustments (doubling/halving wiper setting) ....... 21 digital input/output configuration ........................................ 22 multiple devices on one bus ................................................... 22 terminal voltage operation range ......................................... 23 power - up and power - down sequences .................................. 23 layout and power supply biasing ............................................ 23 digital potentiometer operation ............................................. 24 programmable rheostat operation ......................................... 24 programmab le potentiometer operation ............................... 25 applications information .............................................................. 26 rgb led backlight controller for lcd panels .................... 26 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 29 revision history 9/12 rev. b to rev. c change d temperature range from C 40c to +8 5c to C 40c to +10 5c (throughout) .................................................................. 1 change d wp leakage current from 5 a to 8 a , table 1 ........ 4 change d wp leakage current from 5 a to 8 a, table 2 ........ 5 changes to figure 11 and figure 12 ............................................. 12 changes to order ing guide .......................................................... 29 10/0 9 rev. a to rev. b change to figure 27 ....................................................................... 15 9/05 rev. 0 to rev. a change to figure 6 ......................................................................... 10 change to eemem write protection se ction ............................ 18 changes to figure 37 ...................................................................... 22 deleted table 13 and table 14 ...................................................... 24 change to figure 43 ....................................................................... 25 changes to ordering guide .......................................................... 29 5/03 revision 0: initial version
data sheet ad5253/ad5254 rev. c | page 3 of 32 electrical character istics 1 k ? version v dd = +3 v 10% or +5 v 10%, v ss = 0 v or v dd /v ss = 2.5 v 10%, v a = v dd , v b = 0 v, C 40c < t a < +10 5c, unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mo de resolution n ad5253 6 bits ad5254 8 bits resistor differential nonlinearity 2 r - dnl r wb , r wa = nc, v dd = 5.5 v, ad5253 C 0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5254 C 1.00 0.25 +1.00 lsb r wb , r wa = nc, v dd = 2.7 v, ad5253 C 0. 75 0.30 +0.75 lsb r wb , r wa = nc, v dd = 2.7 v, ad5254 C 1.5 0.3 +1.5 lsb resistor nonlinearity 2 r - inl r wb , r wa = nc, v dd = 5.5 v, ad5253 C 0.5 0.2 +0.5 lsb r wb , r wa = nc, v dd = 5.5 v, ad5254 C 2.0 0.5 +2.0 lsb r w b , r wa = nc, v dd = 2.7 v, ad5253 C 1.0 +2.5 +4.0 lsb r wb , r wa = nc, v dd = 2.7 v, ad5254 C 2 +9 +14 lsb nominal resistor tolerance r ab /r ab t a = 25c C 30 +30 % resistance temperature coefficient (r ab /r ab ) 10 6 /t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel - resistance matching r ab1 /r ab2 0.15 % dc characteristics potentiometer divider mode differential nonlinearity 3 dnl ad5253 C 0.5 0.1 +0.5 lsb ad5254 C 1.00 0.25 +1.00 l sb integral nonlinearity 3 inl ad5253 C 0.5 0.2 +0.5 lsb ad5254 C 2.0 0.5 +2.0 lsb voltage divider temp co (v w /v w ) 10 6 /t code = half scale 25 ppm/c full - scale error v wfse code = full scale, v dd = 5.5 v, ad5253 C 5 C 3 0 lsb code = full scale, v dd = 5.5 v, ad5254 C 16 C 11 0 lsb code = full scale, v dd = 2.7 v, ad5253 C 6 C 4 0 lsb code = full scale, v dd = 2.7 v, ad5254 C 23 C 16 0 lsb zero - scale error v wzse code = zero scale, v dd = 5.5 v, ad5253 0 3 5 lsb cod e = zero scale, v dd = 5.5 v, ad5254 0 11 16 lsb code = zero scale, v dd = 2.7 v, ad5253 0 4 6 lsb code = zero scale, v dd = 2.7 v, ad5254 0 15 20 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 a, b c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 w c w f = 1 khz, measured to gnd, code = half scale 95 pf common - mode leakage current i cm v a = v b = v dd /2 0.01 1.00 a
ad5253/ad5254 data sheet rev. c | page 4 of 32 parameter symbol conditions min typ 1 max unit digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 8 a a0 leakage current i a0 a0 = gnd 3 a input lea kage current (other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf power supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd / v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = C 2.5 v C 5 C 15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd 35 ma eemem dat a restoring mode current 6 i dd_restore v ih = v dd or v il = gnd 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss v dd = 5 v 10% ?0.025 +0.010 +0.025 %/% v dd = 3 v 10% C 0.04 +0.02 +0.04 %/% dynam ic characteristics 5 , 8 bandwidth C 3 db bw r ab = 1 k? 4 mhz total harmonic distortion thd v a =1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v 0.2 s resistor noise voltage e n_wb r w b = 500 ?, f = 1 khz (thermal noise only) 3 nv / hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full - scale change C 80 db analog coupling c at signal input at a0 and measure the output at w1, f = 1 khz C 72 db 1 typical values represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum and minimum resistance wiper position s. r - dnl is the relative step change from an ideal valu e measured between successive tap positions. parts are guaranteed monotonic, except r - dnl of ad5254 1 k? version at v dd = 2.7 v, i w = v dd /r for both v dd = 3 v and v dd = 5 v. 3 inl and dnl are measured at v w with the rdac configured as a potentiometer divid er similar to a voltage output digital - to - analog converter. v a = v dd and v b = 0 v. dnl s pecification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 4 resistor terminal a, terminal b, and terminal w have no limitations on polarity w ith respect to each other. 5 guaranteed by design and not subject to production test. 6 command 0 nop should be activated after command 1 to minimize i dd_restore current consumption. 7 p diss is calculated from i dd v dd = 5 v . 8 all dynamic characteristics use v dd = 5 v.
data sheet ad5253/ad5254 rev. c | page 5 of 32 10 k ?, 50 k ?, 100 k ? versions v dd = +3 v 10% or +5 v 10%, v ss = 0 v or v dd /v ss = 2.5 v 10%, v a = v dd , v b = 0 v, C 40c < t a < + 10 5c, unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characterist ics rheostat mode resolution n ad5253/ad5254 6/8 bits resistor differential nonlinearity 2 r - dnl r wb , r wa = nc, ad5253 ?0.75 0.10 +0.75 lsb r wb , r wa = nc, ad5254 ?1.00 0.25 +1.00 lsb resistor nonlinearity 2 r - inl r wb , r wa = nc, ad5253 ?0.75 0.25 +0.75 lsb r wb , r wa = nc, ad5254 ?2.5 1.0 +2.5 lsb nominal resistor tolerance r ab /r ab t a = 25c ?20 +20 % resistance temperature coefficient (r ab /r ab ) 10 6 /t 650 ppm/c wiper resistance r w i w = 1 v/r, v dd = 5 v 75 130 ? i w = 1 v/r, v dd = 3 v 200 300 ? channel - resistance matching r ab1 /r ab2 r ab = 10 k?, 50 k? 0.15 % r ab = 100 k? 0.05 % dc characteristics potentiometer divider mode differential nonlinearity 3 dnl ad5253 ?0.5 0.1 +0.5 lsb ad5254 ?1.0 0.3 +1.0 lsb integral nonlinearity 3 inl ad5253 ?0.50 0.15 +0.50 lsb ad5254 ?1.5 0.5 +1.5 lsb voltage divider temperature coefficient (v w /v w ) 10 6 /t code = half scale 15 ppm/c full - scale error v wfse code = full scale, ad5253 ?1.0 ?0.3 0 lsb code = full scale, ad5254 ?3 ?1 0 lsb zero - scale error v wzse code = zero scale, ad5253 0 0.3 1.0 lsb code = zero scale, ad5254 0 1.2 3.0 lsb resistor terminals voltage range 4 v a , v b , v w v ss v dd v capacitance 5 a, b c a , c b f = 1 khz, measured to gnd, code = half scale 85 pf capacitance 5 w c w f = 1 khz, measured to gnd, code = half scale 95 pf common - mode leakage current i cm v a = v b = v dd /2 0.01 1 a digital inputs and outputs input logic high v ih v dd = 5 v, v ss = 0 v 2.4 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 2.1 v input logic low v il v dd = 5 v, v ss = 0 v 0.8 v v dd /v ss = +2.7 v/0 v or v dd /v ss = 2.5 v 0.6 v output logic high (sda) v oh r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 4.9 v output logic low (sda) v ol r pull - up = 2.2 k? to v dd = 5 v, v ss = 0 v 0.4 v wp leakage current i wp wp = v dd 8 a a0 leakage current i a0 a0 = gnd 3 a input leakage current (other than wp and a0) i i v in = 0 v or v dd 1 a input capacitance 5 c i 5 pf
ad5253/ad5254 data sheet rev. c | page 6 of 32 parameter symbol conditions min typ 1 max unit power supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply power range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 5 15 a negative supply current i ss v ih = v dd or v il = gnd, v dd = 2.5 v, v ss = ? 2.5 v ?5 ?15 a eemem data storing mode current i dd_store v ih = v dd or v il = gnd, t a = 0c to 10 5c 35 ma eemem data restoring mode current 6 i dd_restore v ih = v dd or v il = gnd, t a = 0c to 10 5c 2.5 ma power dissipation 7 p diss v ih = v dd = 5 v or v il = gnd 0.075 mw power supply sensitivity pss v dd = 5 v 10% ?0.005 +0.002 +0.005 %/% v dd = 3 v 10% ?0.010 +0.002 +0.010 %/% dynamic characteristics 5 , 8 C 3 db bandwidth bw r ab = 10 k?/50 k?/100 k? 400 /80/40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = v dd , v b = 0 v, r ab = 10 k?/50 k?/100 k? 1.5/7/14 s resistor noise voltage e n_wb r ab = 10 k?/50 k?/100 k?, code = midscale, f = 1 khz (ther mal noise only) 9/20/29 nv / hz digital crosstalk c t v a = v dd , v b = 0 v, measure v w with adjacent rdac making full - scale change ?80 db analog coupling c at signal input at a0 and measure output at w1, f = 1 khz ?72 db 1 typical values represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum and minimum resistance wiper pos it ions. r - dnl is the relative step change from an ideal value measured between successive tap positions. parts are guaranteed monotonic, except r - dnl of ad5254 1 k? version at v dd = 2.7 v, i w = v dd /r for both v dd = 3 v and v dd = 5 v. 3 inl and dnl are measured at v w with the r dac configured as a potentiometer divide r, similar to a voltage output d a c . v a = v dd and v b = 0 v. dnl s pecification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 4 resistor terminal a, terminal b, and terminal w have no limitatio ns on polarity with respect to each other. 5 guaranteed by design and not subject to production test. 6 command 0 nop should be activated after command 1 to minimize i dd_restore current consumption. 7 p diss is calculated from i dd v dd = 5 v . 8 all dynamic characteristics use v dd = 5 v.
data sheet ad5253/ad5254 rev. c | page 7 of 32 interface timing characteristics all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using both v dd = 3 v and 5 v. table 3. parameter 1 symbol conditions min typ 2 max unit interface timing scl clock frequency f scl 400 khz t buf bus-free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta set-up time for start condition t 5 0.6 s t hd;dat data hold time t 6 0 0.9 s t su;dat data set-up time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto set-up time for stop condition t 10 0.6 s eemem data storing time t eemem_store 26 ms eemem data restoring time at power-on 3 t eemem_restore1 v dd rise time dependent. measure without decoupling capacitors at v dd and v ss . 300 s eemem data restoring time upon restore command or reset operation 3 t eemem_restore2 v dd = 5 v. 300 s eemem data rewritable time 4 t eemem_rewrite 540 s flash/ee memory reliability endurance 5 100 k cycles data retention 6, 7 100 years 1 see figure 23 for location of measured values. 2 typical values represent av erage readings at 25c and v dd = 5 v. 3 during power-up, all outputs are preset to midscale before restoring the eemem contents. rdac0 has the shortest eemem restore time, whereas rdac3 has the longest. 4 delay time after power-on or reset before new eemem data to be written. 5 endurance is qualified to 100,000 cycles per jedec std. 22 method a117 and measure d at C40c, +25c, an d +105c; typical endur ance at +25c is 700,000 cycles. 6 retention lifetime equivalent at junction temperature t j = 55c per jedec std. 22, method a117. retention lifet ime based on an activation energy of 0.6 ev derates with junction temperature. 7 when the part is not in operation, the sda and scl pins should be pulled high. when these pins are pulled low, the i 2 c interface at these pins conducts a current of about 0.8 ma at v dd = 5.5 v and 0.2 ma at v dd = 2.7 v.
ad5253/ad5254 data sheet rev. c | page 8 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted table 4 . parameter rating v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v dd to v ss 7 v v a , v b , v w to gnd v ss , v dd maximum current i wb , i wa pulsed 20 ma i wb continuous (r wb 1 k?, a open) 1 5 ma i wa continuous (r wa 1 k?, b open) 1 5 ma i ab cont inuous (r ab = 1 k?/10 k?/50 k?/100 k?) 1 5 ma/500 a/ 100 a/50 a digital inputs and output voltage to gnd 0 v, 7 v operating temperature range ?40c to + 10 5c maximum junction temperature (t j max ) 150c storage t emperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c vapor phase (60 sec) 215c infrared (15 sec) 220c tssop - 20 thermal resistance 2 ja 143c/w 1 maxim um terminal current is bound by the maximum applied voltage across any two of the a, b, and w termina ls at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. v dd = 5 v. 2 package p ower d issipation = (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent dam age to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for e xtended periods may affect device reliability. esd caution
data sheet ad5253/ad5254 rev. c | page 9 of 32 pin configuration an d function descripti ons ad5253/ ad5254 top view (not to scale) w0 1 b0 2 a0 3 ad0 4 5 w1 6 b1 7 a1 8 sda 9 v ss 10 v dd w3 b3 a3 ad1 20 19 18 17 16 dgnd scl w2 b2 a2 15 14 13 12 11 03824-0-002 wp figure 2 . pin configuration table 5 . pin function descriptions pin o. mnemonic desc ription 1 w0 wiper terminal of rdac0. v ss v w0 v dd . 2 b0 b terminal of rdac0. v ss v b0 v dd . 3 a0 a terminal of rdac0. v ss v a0 v dd . 4 ad0 i 2 c device address 0. ad0 and ad1 allow four ad5253/ad5254 device s to be addressed. 5 wp write protect, active low. v wp v dd + 0.3 v. 6 w1 wiper terminal of rdac1. v ss v w1 v dd . 7 b1 b terminal of rdac1. v ss v b1 v dd . 8 a1 a terminal of rdac1. v ss v a1 v dd . 9 sda serial data input/output pin. shifts in one bit at a time u pon positive clock edges. msb loaded first. open - drain mosfet requires pull - up resistor. 10 v ss negative supply. connect to 0 v for single supply or C 2.7 v for dual supply, where v dd C v ss + 5.5 v. if v ss is used rather than grounded in dual supply, v ss must be able to sink 35 ma for 26 ms when storing data to eemem. 11 a2 a terminal of rdac2. v ss v a2 v dd . 12 b2 b terminal of rdac2. v ss v b2 v dd . 13 w2 wiper terminal of rdac2. v ss v w2 v dd . 14 scl serial input register clock pin. shifts in o ne bit at a time upon positive clock edges. v scl ( v dd + 0.3 v). pull - up resistor is recommended for scl to ensure minimum power. 15 dgnd digital ground. connect to system analog ground at a single point. 16 ad1 i 2 c device address 1. ad0 and ad1 allow f our ad5253/ad5254 device s to be addressed. 17 a3 a terminal of rdac3. v ss v a3 v dd . 18 b3 b terminal of rdac3. v ss v b3 v dd . 19 w3 wiper terminal of rdac3. v ss v w3 v dd . 20 v dd positive power supply pin. connect +2.7 v to +5 v for single suppl y or 2.7 v for dual supply, where v dd C v ss + 5.5 v. v dd must be able to source 35 ma for 26 ms when storing data to eemem.
ad5253/ad5254 data sheet rev. c | page 10 of 32 typical performance characteristics r-inl (lsb) code (decimal) 03824-0-015 t a = ? 40 c, +25 c, +85 c, +125 c ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 figure 3. r - inl vs. code r-dnl (lsb) code (decimal) 03824-0-016 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ? 40 c, +25 c, +85 c, +125 c figure 4. r - dnl vs. code inl (lsb) code (decimal) 03824-0-017 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ? 40 c, +25 c, +85 c, +125 c figure 5 . inl vs. code dnl (lsb) code (decimal) 03824-0-018 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 0 32 64 96 128 160 192 224 256 t a = ? 40 c, +25 c, +85 c, +125 c figure 6 . dnl vs. code i dd (a) temperature (c) 03824-0-019 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 100 120 i dd @ v dd = +5.5v i dd @ v dd = +2.7v i ss @ v dd = +2.7v, v ss = ?2.7v figure 7 . supply current vs. temperature digital input voltage (v) 03824-0-020 0.0001 0.01 0.001 0.1 1 10 0 1 2 3 4 5 6 v dd = 5.5v v dd = 2.7v i dd (ma) figure 8 . supply current vs. digital input voltage, t a = 25c
data sheet ad5253/ad5254 rev. c | page 11 of 32 r wb ( ? ) v bias (v) 03824-0-021 20 0 40 60 80 100 120 140 160 200 240 180 220 1 0 23456 v dd = 2.7v t a = 25 ?c v dd = 5.5v t a = 25 ?c data = 0x00 figure 9. wiper resistance vs. v bias temperature (?c) 03824-0-022 ?6 ?4 ?2 0 2 4 6 ?40 ?20 0 20 40 60 80 100 120 ? r wb (%) figure 10. change of r wb vs. temperature code (decimal) 03824-0-023 0 32 64 96 128 160 10k ? 100k ? 50k ? 192 224 256 rheostat mode tempco (ppm/c) v dd = 5v t a = ?40c to +85c v a = v dd v b = 0v 500 550 600 650 700 750 800 850 900 950 1000 figure 11. rheostat mode tempco (?r wb /r wb )/?t 10 6 vs. code code (decimal) 03824-0-024 0 20 25 10 5 15 30 35 40 45 50 0 32 64 96 128 160 192 224 256 potentiometer mode tempco (ppm/c) 100k ? 50k ? 10k ? v dd = 5v t a = ?40c to +85c v a = v dd v b = 0v figure 12. potentiometer mode tempco (?v wb /v wb )/?t 10 6 vs. code ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-025 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 13. gain vs. frequency vs. code, r ab = 1 k, t a = 25c ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-026 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 14. gain vs. frequency vs. code, r ab = 10 k, t a = 25c
ad5253/ad5254 data sheet rev. c | page 12 of 32 ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-027 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 15. gain vs. frequency vs. code, r ab = 50 k, t a = 25c ?60 ?48 ?24 ?12 0 ?36 ?54 ?30 ?18 ?6 ?42 gain (db) 1k 10k 10 100 100k 1m 10m frequency (hz) 03824-0-028 0xff 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 0x00 figure 16. gain vs. frequency vs. code, r ab = 100 k, t a = 25c ? r ab ( ? ) code (decimal) 03824-0-029 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 32 64 96 128 160 192 224 256 100k ? 10k ? 50k ? v dd = 5.5v 1k ? figure 17. r ab vs. code, t a = 25c clock frequency (hz) 03824-0-030 0 0.6 0.4 0.2 0.8 1.0 1.2 1 100 10 1k 10k 100k 1m 10m v dd = 2.7v t a = 25c v dd = 5.5v i dd (ma) figure 18. supply current vs. digital input clock frequency 03824-0-031 digital feedthrough clk v dd = 5v v w midscale transition 7fh ? 80h 400ns/div figure 19. clock feedthrough and midscale transition glitch 03824-0-046 v wb0 (0xff stored in eemem) v wb3 (0xff stored in eemem) v dd = va0 = va3 = 3.3v gnd = vb0 = vb3 midscale preset restore rdac0 setting to 0xff restore rdac3 setting to 0xff v dd (no de- coupling caps) midscale preset figure 20. t eemem_restore of rdac0 and rdac3
data sheet ad5253/ad5254 rev. c | page 13 of 32 code (decimal) 03824-0-033 0 3 2 1 4 5 6 0 8 16 24 32 40 48 56 64 theoretical i wb_max (ma) r ab = 1k ? v a = v b = open t a = 25 c r ab = 10k ? r ab = 50k ? r ab = 100k ? figure 21 . ad5253 i wb_max vs. code code (decimal) 03824-0-034 0 3 2 1 4 5 6 0 32 64 96 128 160 192 224 256 theoretical i wb_max (ma) r ab = 1k ? v a = v b = open t a = 25 c r ab = 10k ? r ab = 50k ? r ab = 100k ? figure 22 . ad5254 i wb_max vs. code
ad5253/ad5254 data sheet rev. c | page 14 of 32 i 2 c interface 03824-0-003 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p figure 23. i 2 c interface timing diagram i 2 c interface general description from master to slave from slave to master s = start condition p = stop condition a = acknowledge (sda low) a = not acknowledge (sda high) r/ w = read enable at high; write enable at low r/w a/a s slave address (7-bit) a 0 write a instructions (8-bit) data transferred (n bytes + acknowledge) data (8-bit) p 03824-0-004 figure 24. i 2 cmaster writing data to slave r/w a s slave address (7-bit) 1 read data transferred (n bytes + acknowledge) data (8-bit) data (8-bit) p 03824-0-005 a a figure 25. i 2 cmaster reading data from slave r/w r/w s slave address (7-bit) read or write (n bytes + acknowledge) slave address data a s 03824-0-006 repeated start read or write direction of transfer may change at this point a a/a (n bytes + acknowledge) data p a/a figure 26. i 2 ccombined write/read
data sheet ad5253/ad5254 rev. c | page 15 of 32 i 2 c interface detail d escript ion from master to slave from slave to master s = start condition p = stop condition a = a cknowledge (sda low) a = not acknowledge (sda high) ad1, ad0 = i 2 c d evice a ddress b its , m ust match with the logic states at pins ad1, ad0 r/ w = r ead e nable b it at l ogic high; write enable bit at logic low cmd/ reg = c ommand e nable b it at l ogic h igh ; register access bit at logic low ee/ rdac = eemem r egister at l ogic h igh ; rda c register at logic low a4, a3, a2, a1, a0 = rdac/eemem register addresses 0 write 03824-0-007 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 a p d at a 0 (1 byte + acknowledge) sl a ve address instructions and address cmd/ reg ee/ rdac 0 reg a/ a figure 27 . single write mode 0 write 03824-0-008 s 0 1 0 1 1 a d 1 a d 0 0 a a 4 a 3 a 2 a 1 a 0 p a a rdac_n data rdac_n + 1 data 0 (n byte + acknowledge) slave address instructions and address cmd/ reg ee/ rdac 0 reg a/ a figure 28 . consecutive write mode table 6 . addresses for writing data byte contents to rdac registers (r/ w = 0, cmd/ reg = 0, ee/ rdac = 0) a4 a3 a2 a1 a0 rdac data byte description 0 0 0 0 0 rdac0 6 -/8 - bit wiper setting (2 msb of ad5253 are x) 0 0 0 0 1 rd ac1 6 -/8 - bit wiper setting (2 msb of ad5253 are x) 0 0 0 1 0 rdac2 6 -/8 - bit wiper setting (2 msb of ad5253 are x) 0 0 0 1 1 rdac3 6 -/8 - bit wiper setting (2 msb of ad5253 are x) 0 0 1 0 0 reserved : : : : : : : : : : : : 0 1 1 1 1 reserved
ad5253/ad5254 data sheet rev. c | page 16 of 32 rd ac/eemem write setting the wiper position requires an rdac write operation. the single write operation is shown in figure 27 , and the consecutive write operation is shown in figure 28 . in the consecuti ve write operation, if the rdac is selected and the address starts at 0, the first data byte goes to rdac0, the second data byte goes to rdac1, the third data byte goes to rdac2, and the fourth data byte goes to rdac3. this operation can be continued for up to eight addresses with four unused addresses; it then loops back to rdac0. if the address starts at any of the eight valid addresses, n, the data first goes to rdac_n, rdac_n + 1, and so on; it loops back to rdac0 after the eighth address. the rdac address is shown in table 6 . while the rdac wiper setting is controlled by a specific rdac register, each rdac register corresponds to a specific eemem location, which provides nonvolatile wiper storage funct ionality. the addresses are shown in table 7 . the single and consecutive write operations also apply to eemem write operations. there are 12 nonvolatile memory locations: eemem4 to eemem15. users can store 12 bytes of information , such as memory data for other components, look - up table s , or system identification information. in a write operation to the eemem registers, the device disables the i 2 c interface during the internal write cycle. acknowledge polling is required to determi ne the completion of the write cycle. see the eemem write - acknowledge polling section. rdac/eemem read the ad5253/ad5254 provide two different rdac or eemem read operations. for example, figure 29 shows the method of reading the rdac0 to rdac3 contents without specifying the address, assuming a ddress rdac0 was already selected in the previous operation. if an rdac_n address other than rdac0 was previously selected, readback starts with a ddress n, followe d by n + 1, and so on. figure 30 illustrates a random rdac or eemem read operation. this operation allows users to specify which rdac or eemem register is read by issuing a dummy write command to change the rdac address pointer a nd then proceeding with the rdac read operation at the new address location. table 7 . addresses for writing (storing) rdac settings and user - defined data to eemem registers (r/ w = 0, cmd/ reg = 0, ee/ rdac = 1) a4 a3 a2 a1 a0 data byte descrition 0 0 0 0 0 store rdac0 s etting to eemem0 1 0 0 0 0 1 store rdac1 s etting to eemem1 1 0 0 0 1 0 store rdac2 s etting to eemem2 1 0 0 0 1 1 store rdac3 s etting to eemem3 1 0 0 1 0 0 store u ser d ata to eemem4 0 0 1 0 1 store u ser d ata to eemem5 0 0 1 1 0 store u ser d ata to eemem6 0 0 1 1 1 store u ser d ata to eemem7 0 1 0 0 0 store u ser d ata to eemem8 0 1 0 0 1 store u ser d ata to eemem9 0 1 0 1 0 store u ser d ata to eemem10 0 1 0 1 1 store u ser d ata to eemem11 0 1 1 0 0 store u ser d ata to eemem12 0 1 1 0 1 store u ser d ata to eemem13 0 1 1 1 0 store u ser d ata to eemem14 0 1 1 1 1 store u ser d ata to eemem15 table 8 . addresses for reading (restoring) rdac settings and user data from eemem (r/ w = 1, cmd/ reg = 0, ee/ rdac = 1) a4 a 3 a2 a1 a0 data byte descrition 0 0 0 0 0 read rdac0 setting from eemem0 0 0 0 0 1 read rdac1 setting from eemem1 0 0 0 1 0 read rdac2 setting from eemem2 0 0 0 1 1 read rdac3 setting from eemem3 0 0 1 0 0 read user d ata from eemem4 0 0 1 0 1 read u ser d ata from eemem5 0 0 1 1 0 read u ser d ata from eemem6 0 0 1 1 1 read u ser d ata from eemem7 0 1 0 0 0 read u ser d ata from eemem8 0 1 0 0 1 read u ser d ata from eemem9 0 1 0 1 0 read u ser d ata from eemem10 0 1 0 1 1 read u ser d ata from eemem11 0 1 1 0 0 read u ser d ata from eemem12 0 1 1 0 1 read u ser d ata from eemem13 0 1 1 1 0 read u ser d ata from eemem14 0 1 1 1 1 read u ser d ata from eemem15 1 user s can store any of the 64 rda c settings for ad5253 or any of the 256 rdac settings for the ad5254 directly to the eemem . this is not limited to current rdac wiper setting.
data sheet ad5253/ad5254 rev. c | page 17 of 32 from master to slave from slave to master s = s tart c ondition p = s top c ondition a = a cknowledge (sda l ow) a = n ot a cknowledge (sda h igh) ad1, ad0 = i 2 c d evice a ddress b its , m ust match with th e logic states at pins ad1, ad0 r/ w = r ead e nable bit at l ogic high; w rite e nable bit at l ogic low cmd/ reg = c ommand e nable b it at l ogic h igh ; r egister a ccess b it at l ogic low c3, c2, c1, c0 = c ommand b its a2, a1, a0 = rdac/eemem r egister a ddresses 1 read 03824-0-009 s 0 1 0 1 1 a d 1 a d 0 1 a p a rdac_n or eemem_n register data rdac_n + 1 or eemem_n + 1 register data slave address (n bytes + acknowledge) a figure 29 . rdac current read (restricted to previously selected address stored in the register) p s slave address 0 write slave address instructional and address a 1 s 03824-0-010 repeated start 1 read a 0 a (n bytes + acknowledge) rdac or eemem data a/a figure 30 . rdac or eemem random read 0 write 03824-0-011 1 cmd s 0 1 0 1 1 a d 1 a d 0 0 a c 3 c 2 c 1 c 0 a 2 a 1 a 0 a p rdac slave address cmd/ reg figure 31 . rdac quick command write (dummy write)
ad5253/ad5254 data sheet rev. c | page 18 of 32 rdac/eemem quick commands the ad5253/ad5254 feature 12 quick commands that fac ilitate easy manipulation of rdac wiper settings and provide rdac - to - eemem storing and restoring functions. the command format is shown in figure 31 , and the command descriptions are shown in table 9 . w hen using a quick command, issuing a third byte is not needed, but is allowed. the quick commands reset and store rdac to eemem require acknowledge polling to determine whether the command has finished executing. r ab tolerance stored in read - only memory t he ad5253/ad5254 feature patented r ab tolerances storage in the nonvolatile memory. the tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. the knowledge of the stored tolerance, which is th e average of r ab over all codes ( see figure 16 ), allows users to predict r ab accurately. this feature is valuable for precision, rheostat mode, and open - loop applications, in which knowledge of absolute resistance is critical. t he stored tolerances reside in the read - onl y memory and are expressed as percentage s. each tolerance is 16 bits long and is stored in two memory locations (see table 10 ). the tolerance data is expressed in sign magnitude binary format stored in two bytes; an example is shown in figure 32 . for the first byte in r egister n, the msb is designated for the sign (0 = + and 1 = C ) and the 7 lsb is designated for the integer portion of the tolerance. for the s econd byte in r egister n + 1 , all eight data bits are designated for the decimal portion of tolerance. as shown in table 10 and figure 32 , for example, if the rated r ab is 10 k? and the data readback f rom address 1 1000 shows 0001 1100 and address 11001 shows 0 000 1111, then rdac0 tolerance can be calculated as msb: 0 = + next 7 msb: 001 1100 = 28 8 lsb: 0000 1111 = 15 2 C 8 = 0.06 tolerance = 28.06% and, therefore, r ab_actual = 12.806 k? eemem write - ack nowledge polling after each write operation to the eemem registers, an internal write cycle begins. the i 2 c interface of the device is disabled. to determine if the internal write cycle is complete and the i 2 c interface is enabled, interface polling can be executed. i 2 c interface polling can be conducted by sending a start condition followed by the slave address and the write bit. if the i 2 c interface responds with an ack, the write cycle is complete and the interface is ready to proceed with further operat ions. other - wise, i 2 c interface polling can be repeated until it succeeds. command 2 and command 7 also require acknowledge polling. eemem write protection setting the wp pin to logic low after eemem programming protects the memory a nd rdac registers from future write operations. in this mode, the eemem and rdac read operations function as normal. table 9 . rdac -to - eemem interface and rdac operation quick command bits (cmd/ reg = 1, a2 = 0) c3 c2 c1 c0 command description 0 0 0 0 nop 0 0 0 1 restore eemem (a1, a0) to rdac (a1, a0) 1 0 0 1 0 store rdac (a1, a0) to eemem (a1, a0) 0 0 1 1 decrement rdac (a1, a0) 6 db 0 1 0 0 decrement all rdacs 6 db 0 1 0 1 decrement rdac (a1, a0) one st ep 0 1 1 0 decrement all rdacs one step 0 1 1 1 reset: restore eemems to all rdacs 1 0 0 0 increment rdacs (a1, a0) 6 db 1 0 0 1 increment all rdacs 6 db 1 0 1 0 increment rdacs (a1, a0) one step 1 0 1 1 increment all rdacs one step 1 1 0 0 reserve d : : : : : : : : : : 1 1 1 1 reserved 1 this command leaves the device in the eemem r ead power state , which consumes power. i ssue the nop command to re turn the device to its idle state.
data sheet ad5253/ad5254 rev. c | page 19 of 32 table 10 . address table for reading tolerance (cmd/ reg = 0, ee/ rdac = 1, a4 = 1) a4 a3 a2 a1 a0 data byte description 1 1 0 0 0 sign and 7 - bit integer values of rdac0 tolerance (read only) 1 1 0 0 1 8 - bit decimal value of rdac0 tolerance (read only) 1 1 0 1 0 sign and 7 - bit integer values of rdac1 tolerance (read only) 1 1 0 1 1 8 - bit decimal value of rdac1 tolerance (read only) 1 1 1 0 0 sign and 7 - bit integer values of rdac2 tolerance (read only) 1 1 1 0 1 8 - bit decimal value of rdac2 tolerance (read only) 1 1 1 1 0 sign and 7 - bit integer values of rdac3 tolerance (read only) 1 1 1 1 1 8 - bit decimal value of rdac3 tolerance (read onl y) 03824-0-012 a a a d7 d6 d5 d4 d3 d2 d1 d0 sign sign 7 bits for integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits for decimal number 2 ? 8 2 ? 1 2 ? 2 2 ? 3 2 ? 4 2 ? 5 2 ? 6 2 ? 7 figure 32 . format of stored tolerance in sign magnitude format with bit position descriptions (unit is percent , only data bytes are shown)
ad5253/ad5254 data sheet rev. c | page 20 of 32 i 2 c - compatible 2 - wire serial bus sda frame 1 slave address byte frame 2 instruction byte scl ack. by ad525x ack. by ad525x ack. by ad525x frame 1 data byte stop by master 03824-0-013 start by master 0 1 1 0 1 1 ad1 ad0 r/w x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 9 1 9 1 9 figure 33 . general i 2 c write pattern 03824-0-014 sda frame1 slave address byte frame 2 rdac register scl ack. by ad525x no ack. by master stop by master start by master 0 1 1 0 1 1 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 9 1 9 r/w figure 34 . general i 2 c read pattern the first byte of the ad5253/ad5254 is a slave address byte (see figure 33 and figure 34 ). it has a 7 - bit slave address an d an r/ w bit. the 5 msb of the slave address is 01011, and the next 2 lsb is determined by the states of the ad1 and ad0 pins. ad1 and ad0 allow the user to place up to four ad5253/ad5254 device s on one bus. ad5253/ad5254 can be controll ed via an i 2 c - compatible serial bus and are connected to this bus as slave devices. the 2 - wire i 2 c serial bus protocol (see figure 33 and figure 34 ) follows: 1. the master initiates a data transfer by esta blishing a start condition, such that sda goes from high to low while scl is high (see figure 33 ). the following byte is the slave address by te, which consists of the 5 msb of a slave address defined as 01011. the next two bits a re ad1 and ad0, i 2 c device address bits. depending on the states of their ad1 and ad0 bits, four ad5253/ad5254 device s can be addressed on the same bus. the last lsb, the r/ w bit, determines whether data is read from or written to the sla ve device. the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is called an acknowledge bit). at this stage, all other devices on the bus remain idle while the selected d evice waits for data to be written to or read from its serial register. 2. in the write mode (except when restoring eemem to the rdac register), there is an instruction byte that follows the slave address byte. the msb of the instruction byte is labeled cmd/ reg . msb = 1 enables cmd, the command instruction byte; msb = 0 enables general register writing. the third msb in the instruction byte, labeled ee/ rdac , is true when msb = 0 or when the device is in general wri ting mode. ee enables the eemem register, and reg enabl es the rdac register. the 5 lsb , a4 to a0, designate s the addresses of the eemem and rdac registers (see figure 27 and figure 28 ). when msb = 1 or when the device is in cmd mode, the four bits following the msb are c3 to c1, which correspond to 12 predefined eemem controls and quick commands; there are also four facto ry - reserved commands. the 3 lsb a2, a1, and a0 are 4 - channel rdac addresses (see figure 31 ). after acknowledging the instruction byte, the last byte in the write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowl edge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 33 ). 3. in current read mode, the rdac0 data byte immediately follows the acknowledgmen t of the slave address byte. after an acknowledgement, rdac1 follows, then rdac2, and so on. (there is a slight difference in write mode, where the last eight data bits representing rdac3 data are followed by a no acknowledge bit.) similarly, the transitio ns on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 34 ). another reading method, random read method, is shown in figure 30. 4. when all da ta bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line that occurs while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 33 ). in read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the sda line remains high. the master brings the sda line low before the 10 th clock pulse and then brings the sda line high to establish a stop condition (see figure 34 ).
data sheet ad5253/ad5254 rev. c | page 21 of 32 theory of operation the ad5253/ad5254 are quad - channel digital potentiometers in 1 k ? , 10 k ? , 50 k ? , or 100 k ? that allow 64/256 linear resis - ta nce step adjustments. the ad5253/ad5254 employ double - gate cmos eeprom technology, which allows resistance settings and user - defined data to be stored in the eemem registers. the eemem is nonvolatile , such that settings remain when power is removed. the rd ac wiper settings are restored from the nonvolatile memory settings during device power - up and can also be restored at any time during operation. the ad5253/ad5254 resistor wiper positions are determined by the rdac register contents. the rdac register ac ts like a scratch - pad register, allowing unlimited changes of resistance settings. rdac register contents can be changed using the devices serial i 2 c interface. the format of the data - words and the commands to program the rdac registers are discussed in t he i 2 c interface section. the four rdac registers have corresponding eemem memory locations that provide nonvolatile storage of resistor wiper position settings. the ad5253/ad5254 provide commands to store the rdac register conte nts to their respective eemem memory locations. during subsequent power - on sequences, the rdac registers are automatically loaded with the stored value. whenever the eemem write operation is enabled, the device activates the internal charge pump and raises the eemem cell gate bias voltage to a high level; this essentially erases the current content in the eemem register and allows subsequent storage of the new content. saving data to an eemem register consumes about 35 ma of current and lasts approximately 26 ms. because of charge - pump operation, all rdac channels may experience noise coupling during the eemem writing operation. the eemem restore time in power - up or during operation is about 300 s. note that the power - up eemem refresh time depends on how fa st v dd reaches its final value. as a result, any supply voltage decoupling capacitors limit the eemem restore time during power - up. for example, figure 20 shows the power - up profile of the v dd where there is no decoupling capacit ors and the applied power is a digital signal. the device initially resets the rdacs to midscale before restoring the eemem contents. the omission of the decoupling capacitors should only be considered when the fast restoring time is absolutely needed in t he application. in addition, users should issue a nop command 0 immediately after using command 1 to restore the eemem setting to rdac, thereby minimizing supply current dissipation. reading user data directly from eemem does not require a similar nop comm and execution. in addition to the movement of data between rdac and eemem registers, the ad5253/ad5254 provide other shortcut commands that facilitate programming, as shown in table 11. table 11 . quick com mands comm and description 0 n o p. 1 restore eemem content to rdac. user should issue nop immediately after this command to conserve power. 2 store rdac register setting to eemem. 3 decrement rdac 6 db (shift data bits right). 4 decrement all rdacs 6 db (shift all data bits right). 5 decrement rdac one step. 6 decrement all rdacs one step. 7 reset eemem contents to all rdacs. 8 increment rdac 6 db (shift data bits left). 9 increment all rdacs 6 db (shift all data bits left). 10 increment rdac one s tep. 11 increment all rdacs one step. 12 to 15 reserved. linear increment/dec rement commands the increment and decrement commands (10, 11, 5, and 6) are useful for linear step - adjustment applications. these commands simplify microcontroller software co ding by allowing the controller to send just an increment or decrement command to the ad5253/ad5254. the adjustments can be directed to a single rdac or to all four rdacs. 6 d b adjustments (doubling/halving wi per setting) the ad5253/ad5254 accommodate 6 db adjustments of the rdac wiper positions by shifting the register contents to left/ right for increment/decrement operations, respectively. com - mand 3, command 4, command 8, and command 9 can be used to increment or decrement the wiper positions in 6 db steps synchronously or asynchronously. incrementing the wiper position by +6 db essentially doubles the rdac register value, whereas decrementing the wiper position by C 6 db halves the register content. internally, the ad5253/ad5254 use shift registers to shift the bits left and right to achieve a 6 db increment or decrement. the maximum number of adjustments is nine and eight steps for increment ing from zero scale and decrement ing from full scale, respectively. these functions are useful for various audi o/video level adjustments, especially for white led brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments.
ad5253/ad5254 data sheet rev. c | page 22 of 32 digital input/output configuration sda is a digital input/output with an open - dra in mosfet that requires a pull - up resistor for proper communication. on the other hand, scl and wp are digital inputs for which pull - up resistors are recommended to minimize the mosfet cross - conduction current when the driving signal s are lower than v dd . scl and wp have esd protection diodes, as shown in figure 35 and figure 36. wp can be permanently tied to v dd without a pull - up resist or if the write - protect feature is not used. if wp is left floating, an internal current source pulls it low to enable write protection. in applications in which the device is programmed infrequently, this allows the part to default to write - protection mode after any one - time factory programming or field calibration without using an on - board pull - down resistor. because there are protection diodes on all inputs, the signal levels must not be greater than v dd to prevent forward biasing of the diodes. 03824-0-035 gnd scl v dd figure 35 . scl digital input 03824-0-036 gnd inputs wp v dd figure 36 . equivalent wp digital input multiple devices on one bus the ad5253/ad5254 are equipped with two addressing pins, ad1 and ad0, that allow up to four ad5253/ad5254 device s to be operated on one i 2 c bus. to achieve this result, the states of ad1 and ad0 on each device must first be defined. an example is shown in table 12 and figure 37 . in i 2 c programming, each device is issued a different slave address 01011(ad1)(ad0) to complete the addressing. table 12 . multiple devices addressing ad1 ad0 device addressed 0 0 u1 0 1 u2 1 0 u3 1 1 u4 sda sda ad1 ad0 master scl scl sda ad1 ad0 scl sda ad1 ad0 scl sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5253/ ad5254 ad5253/ ad5254 ad5253/ ad5254 ad5253/ ad5254 03824-0-037 figure 37 . multiple ad5253/ad5254 device s on a single bus in wireless base station smart - antenna systems that require arrays of digital potentiometers to bias the power amplifiers, large numbers of ad5253/ad5254 device s can be addressed b y using extra decoders, switches, and i/o buses, as shown in figure 38 . for example, to communicate to a total of 16 devices, four decoders and 16 sets of combinational switches (four sets shown in figur e 38) are needed. two i/o buses serve as the common inputs of the four 2 4 decoders and select four sets of outputs at each combination. because the four sets of combination switch outputs are unique, as shown in figure 38, a specific device is addressed by proper ly programming the i 2 c with the slave address defined as 01011(ad1)(ad0). this operation allows one of 16 devices to be addressed, provided that the inputs of the two decoders do not change states. the inputs of the de coders are allowed to change once the operation of the specified device is completed.
data sheet ad5253/ad5254 rev. c | page 23 of 32 03824-0-038 +5v r1 ad1 ad0 n1 4 2 ? 4 +5v r2 x ad1 ad0 n2 x +5 p2 y p2 y p3 x r3 x r3 y n3 y ad1 ad0 ad1 ad0 ? 4 ? 4 ? 4 +5v p4 r4 +5v 2 ? 4 decoder 4 2 ? 4 decoder 4 2 ? 4 decoder 4 2 ? 4 decoder figure 38. four devices with ad1 and ad0 of 00 terminal voltage operation range the ad5253/ad5254 are designed with internal esd diodes for protection; these diodes also set the boundaries for the terminal operating voltages. positive signals present on te r m i n a l a , te r m i n a l b, or te r m i n a l w t h at e x c e e d v dd are clamped by the forward-biased diode. similarly, negative signals on te r m i n a l a , te r m i n a l b, or te r m i n a l w t h at are more negative than v ss are also clamped (see figure 39). in practice, users should not operate v ab , v wa , and v wb to be higher than the voltage across v dd to v ss , but v ab , v wa , and v wb have no polarity constraint. 03824-0-039 v dd a w b v ss figure 39. maximum terminal voltages set by v dd and v ss power-up and power-down sequences because the esd protection diodes limit the voltage compliance at te r m i n a l a , te r m i n a l b, a nd te r m i n a l w ( fi g u re 3 9 ) , it i s important to power v dd /v ss before applying any voltage to these terminals. otherwise, the diodes are forward biased such that v dd /v ss are powered unintentionally and may affect the users circuit. similarly, v dd /v ss should be powered down last. the ideal power-up sequence is in the following order: gnd, v dd , v ss , digital inputs, and v a /v b /v w . the order of powering v a , v b , v w , and the digital inputs is not important, as long as they are powered after v dd /v ss . layout and power supply biasing it is always a good practice to employ a compact, minimum lead-length layout design. the leads to the input should be as direct as possible, with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors. low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. figure 40 illustrates the basic supply-bypassing configuration for the ad5253/ad5254. 03824-0-040 v dd v dd v ss v ss gnd c3 ad5253/ad5254 c4 c1 c2 10 ? f 10 ? f 0.1 ? f 0.1 ? f figure 40. power supply- bypassing configuration the ground pin of the ad5253/ad5254 is used primarily as a digital ground reference. to minimize the digital ground bounce, the ad5253/ad5254 ground terminal should be joined remotely to the common ground (see figure 40).
ad5253/ad5254 data sheet rev. c | page 24 of 32 digital potentiomete r operation the structure of the rdac i s designed to emulate the performance of a mechanical potentiometer. the rdac contains a string of resistor segments with an array of analog switches that act as the wiper connection to the resistor array. the number of points is the resolution of the devi ce. for example, the ad5253/ad5254 emulate 64/256 connection points with 64/256 equal resistance, r s , allowing them to provide better than 1.5%/0.4% resolution. figure 41 provides an equivalent diagram of the connections between the three terminals that make up one channel of the rdac. switches sw a and sw b are always on, but only one of switches sw(0) to sw(2 n C 1 ) can be on at a time ( determined by the se tting decoded from the data bit) . because the switches are nonideal, there is a 75 ? wiper resistance, r w . wiper resistance is a function of supply voltage and temperature : l ower supply voltages and higher temperatures result in higher wiper resistances. consideration of wiper resistance dynamics is important in applications in whi ch accurate prediction of output resistance is required. 03824-0-041 sw a a x sw (2 n ? 1) sw (2 n ? 2) sw(1) digital circuitry omiitted for clarity rdac wiper register and decoder sw(0) sw b r s = r ab /2 n b x w x r s r s r s figure 41 . equivalent rdac structure programmable rheosta t operation if either the w - to - b or w - to - a terminal is used as a variable resistor, the unused terminal can be opened or shorted with w; such operation is called rheostat mode (see figure 42 ). the resistance tolerance can range 20%. 03824-0-042 a b w a b w a b w figure 42 . rheostat mode configuration the nominal resistance of the ad5253/ ad5254 has 64/256 contact points accessed by the wiper terminal, plus the b terminal contact. the 6 - /8 - bit data - word in the rdac register is decoded to select one of the 64/256 settings. the wipers first connection starts at the b terminal for data 0x00. this b termi - nal connection has a wiper contact resistance, r w , of 75 ?, regardless of the nominal resistance. the second connection (the ad5253 10 k? part) is the first tap point where r wb = 231 ? (r wb = r ab /64 + r w = 156 ? + 75 ?) for data 0x01, and so on. each lsb data value increase moves the wiper up the resisto r ladder until the last tap point is reached at r wb = 9893 ? . see figure 41 for a simplified diagram of the equivalent rdac circuit. the general equation that determines the digitally programmed output resistance between w and b is ad5253: rwb(d) = (d/64) rab + 75 ? (1) ad5254: rwb(d) = (d/256) rab + 75 ? (2) where: d is the decimal equivalent of the data contained in the rdac latch. r ab is the nominal end - to - end resistance.
data sheet ad5253/ad5254 rev. c | page 25 of 32 r ab (%) d (code in decimal) 03824-0-043 0 25 50 75 100 0 10 32 48 63 r wa r wb figure 43 . ad5253 r wa ( d) and r wb (d) vs. decimal code since the digital potentiometer is not ideal, a 75 ? finite wiper resistance is present that can easily be seen when the device is programmed at zero scale. because of the fine geometric and interconnects employed by the devi ce, care should be taken to limit the current conduction between w and b to no more than 5 ma continuous for a total resistance of 1 k ? or a pulse of 20 ma to avoid degradation or possible dest ruction of the device. the maximum dc current for ad5253 and ad5254 are shown in figure 21 and figure 22 , respectively. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled compl ementary resistance, r wa . when these terminals are used, the b terminal can be opened. the r wa starts at a maximum value and decreases as the data loaded into the latch increases in value (see figure 43 . the general equation for this operation is ad5253: rwa(d) = [(64 C d)/64] rab + 75 ? (3) ad5254: rwa(d) = [(256 C d)/256] rab + 75 ? (4) the typical distribution of r ab from channel - to - channel matches is about 0.15% within a given device. on the other hand, device - to - device matching is process - lot dependent with a 20% tolerance. programmable potenti ometer operation if all three terminals are used, the operation is called potenti - ometer mode (see figure 44 ); the most common configuration is the volt age divider operation. 03824-0-044 a b w v i v c figure 44 . potentiometer mode configuration if the wiper resistance is ignored, the transfer function is simply ad5253: b ab w v v d v + = 64 (5) ad5254: b ab w v v d v + = 256 (6) a more accurate calcu lation that inclu des the wiper resistance effect is a w ab w ab n w v r r r r d d v 2 2 ) ( + + = (7) where 2 n is the number of steps. unlike in rheostat mode operation, where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of d/2 n wit h a relatively small error contributed by the r w terms. therefore, the tolerance effect is almost cancelled. similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/c, except at low value codes where r w dominates. p otentiometer mode operations include other applications such as op amp input, feedback - resistor networks, and other voltage - scaling applications. the a, w, and b terminals can, in fact, be input or output terminals, provided that |v a |, |v w |, and |v b | do no t exceed v dd to v ss .
ad5253/ad5254 data sheet rev. c | page 26 of 32 applications information rgb led backlight co ntroller for lcd panels because high power (>1 w) rgb leds offer superior color quality compared with cold cathode florescent lamps ( ccfls ) as backlighting sources, it is likely that hig h - end lcd panels will employ rgb leds as backlight in the near future. unlike conventional leds, high power leds have a forward voltage of 2 v to 4 v and consume more than 350 ma at maximum brightness. the led brightness is a linear function of the conduct ion current, but not of the forward voltage. to increase the brightness of a given color, multiple leds can be connected in series, rather than in parallel, to achieve uniform brightness. for example, three red leds configured in series require an average of 6 v to 12 v headroom, but the circuit operation requires current control. as a result, figure 45 shows the implementation of one high power rgb led controller using a ad5254, a boost regulator, an op amp, and power mosfets. the adp1610 (u2 in figure 45 ) is an adjustable boost regulator with its output adjusted by the ad5254s rdac3. such an output should be set high enough for proper operation but low enough to conserve power. the adp1610s 1.2 v b and gap reference is buffered to provide the reference level for the voltage dividers set by the ad5254s rdac0 to rdac2 and resistor r2 to resistor r4. for example, by adjusting the ad5254s rdac0, the desirable voltage appears across the sense resistors, r r . if u2s output is set properly, op amp u3a and power mosfet n1 do whatever is necessary to regulate the current of the loop. as a result, the current through the sense resistor and the red leds is r rr r r v i = (8) r8 is needed to prevent o scillation. in addition to the 256 levels of adjustable current/brightness, users can also apply a pwm signal at u3s sd pin to achieve finer brightness resolution or better power efficiency.
data sheet ad5253/ad5254 rev. c | page 27 of 32 03824-0-045 ad8594 u3b u3a ad8594 +5v c10 u3d scl sda r4 r3 r2 c1 22k ? 22k ? 250k ? 250k ? 10k ? 10k ? 10k ? 250k ? 10k ? 10k ? 10k ? 4.7? 0.1? 4.7? 0.1? 4.7? 0.1? 100k ? 10 ? f 390 ? f 0.1? f 10 ? f 10 ? f r7r6 a3 u1 rdac3 clk sdi a2 b2 a1 b1 rdac2 rdac1 a0 l1 - slf6025-100m1r0 d1 - mbr0520lt1 w0 pwm w1 w2 b0 rdac0 gnd ad0 ad1 ad5254 b3 r c r1 r5 u2 d1 db1 db2 db3 dg1 dg2 dg3 dr1 v out dr2 dr3 vb n3 ib ig ir vg vrb n2 c3 r10 rb r9 r8 vrr irfl3103 irfl3103 irfl3103 vr rr rg vrg n1 +5v c11 8 u3c 4 l1 v dd c ss c c v ss v ref = 2.5v 10 ? f 0.1? f ad8594 ad8594 sd v+ v? adp1610 in sw fb comp ss rt gnd sd figure 45. digital potentiomete r-based rgb led controller
ad5253/ad5254 data sheet rev. c | page 28 of 32 outline dimensions compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 46. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters
data sheet ad5253/ad5254 rev. c | page 29 of 32 ordering guide model 1 , 2 , 3 step r ab (k?) temperature range package description package option ordering quantity ad5253bru1 64 1 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bru1 - rl7 64 1 ?40 c to +10 5 c 20- lead tssop ru -20 1,000 ad5253bruz1 64 1 ?40 c to +10 5 c 20- lead tssop ru -20 75 a d5253bruz1 - rl7 64 1 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bru10 64 10 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bru10 - rl7 64 10 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bruz10 64 10 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bruz1 0 - rl7 64 10 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bru50 64 50 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bru50 - rl7 64 50 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bruz50 64 50 ?40 c to + 10 5 c 20 - lead tssop ru - 20 75 ad5253bruz50 - rl7 64 50 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bru100 64 100 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bru100 - rl7 64 100 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5253bruz100 64 100 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5253bruz100 - rl7 64 100 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bru1 256 1 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bru1 - rl7 256 1 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bruz1 256 1 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bruz1 - rl7 256 1 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bru10 256 10 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bru10 - rl7 256 10 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bruz10 256 10 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bruz10 - rl7 256 10 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bru50 256 50 ?40 c to + 10 5 c 20 - lead tssop ru - 20 75 ad5254bru50 - rl7 256 50 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bruz50 256 50 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bruz50 - rl7 256 50 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bru100 256 100 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bru100 - rl7 256 100 ?40 c to + 105 c 20- lead tssop ru -20 1,000 ad5254bruz100 256 100 ?40 c to + 105 c 20- lead tssop ru -20 75 ad5254bruz100 - rl7 256 100 ?40 c to + 105 c 20- lead tssop ru -20 1,000 eval - ad5254sd z 256 evaluation board 1 1 in the package marking, line 1 shows the part number. line 2 shows the branding information, such that b1 = 1 k?, b10 = 10 k?, and so on. there is also a # marking for the pb - free part. line 3 shows the date code in yyww. 2 z = rohs compliant part. 3 the evaluation board is shipped with the 10 k ? r ab resist or option; however, the board is compatible with all available resistor value options.
ad5253/ad5254 data sheet rev. c | page 30 of 32 notes
data sheet ad5253/ad5254 rev. c | page 31 of 32 notes
ad5253/ad5254 data sheet rev. c | page 32 of 32 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the p hilips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2003 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03824 - 0 - 9/12(c)

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